The present invention relates generally to the electrical, electronic and computer arts and, more particularly, to nanosheet transistors and the formation of spacers in such transistors.
With shrinking dimensions of various integrated circuit components, transistors such as field-effect transistors (FETs) have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Metal oxide semiconductor field-effect transistors (MOSFETs) are well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
Nanosheet FETs have been under development for possible use in tight pitch applications such as 7 nm nodes and beyond. Such FETs include multiple channel layers, each channel layer being separated by a gate stack including a layer of electrically conductive gate material and a gate dielectric layer. The gate stacks wrap around all sides of the channel layers, thereby forming a gate-all-around (GAA) structure. Epitaxial regions on the ends of the nanosheet channel layers form source/drain regions of the nanosheet FETs. Spacers are employed for electrically isolating the gates from the source/drain regions of nanosheet transistors.
A sequence of steps that may be employed during fabrication of a nanosheet transistor is shown in FIGS. 1A-1F. The structure 20 shown in FIG. 1A includes a stack of semiconductor layers including silicon layers 21 and silicon germanium layers 22 grown epitaxially in alternating sequence. The semiconductor layers can be formed on a substrate 23 such as a bulk semiconductor (e.g. silicon) substrate or a semiconductor-on-insulator substrate. As shown in FIG. 1B, dummy gates 24 and gate spacers 26 are formed on the top surface of the stack of semiconductor layers. The dummy gates 24 are typically amorphous silicon or polycrystalline silicon. Outer spacers 26 are formed on the dummy gates. A conformal silicon nitride layer may be deposited on the structure and patterned to form the outer spacers. The dummy gates 24 and outer spacers 26 protect the underlying portion of the stack of semiconductor layers while the exposed portions thereof are removed to form columns 25 of semiconductor nanosheets as shown in FIG. 1C. The silicon germanium layers 22 are undercut by a timed etch to form divots 27 between the silicon layers 21, as shown in FIG. 1D. A conformal dielectric layer, for example silicon nitride, is deposited on the structure, thereby filling the divots. The conformal dielectric layer is subjected to a timed etch to remove the dielectric material outside the stack of semiconductor layers. The remaining dielectric material forms inner spacers 28 between the silicon layers 21, as shown in FIG. 1D. Source/drain semiconductor material 29, for example doped silicon germanium, is then epitaxially grown on the exposed end portions of the silicon layers 21. A structure as shown in FIG. 1E is obtained at this stage of the process. A gate stack is formed later in the process between the channel layers (silicon layers 21) of the structure by removing the dummy gate and replacing it with gate materials such as high-k gate dielectric 30 and gate conductor metal 32. A structure as shown in FIG. 1F may be obtained.
The configurations of nanosheet devices as shown in FIG. 1F lead to difficulties in extension formation which can lead to higher access resistance in the devices. The areas in which extension regions are to be formed are indicated by arrows in FIG. 1F.